Flash memory devices perform block erase operations (i.e., erasing an entire block of memory locations at a time), which may take a relatively long time to accomplish. In NAND flash memory systems, block write operations may also take a relatively long time to accomplish. The memory controller, after triggering the flash memory device to perform the erase operation, may then perform operations with other memory devices while this erase or block write operation is being executed within the flash memory device. With current types of NAND flash memory interfaces, there is no efficient way for the memory controller to know when the erase operation is completed. Conventional solutions are to periodically poll the memory device (which is time consuming and inefficient), or to dedicate a separate signal line to each memory device to indicate completion (which adds to the pin count and takes up addition space). When high bandwidth and low pin-count are both important, neither of these alternatives is satisfactory.